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fn7575 rev 5.00 page 1 of 31 september 5, 2012 fn7575 rev 5.00 september 5, 2012 isl12022ma low power rtc with battery bac ked sram, integrated 5ppm temper ature compensation and auto daylight saving datasheet the isl12022ma device is a low power real time clock (rtc) with an embedded temperature sensor and crystal. device functions include oscillator co mpensation, clock/calendar, power fail and low battery monitors, brownout indicator, one-time, periodic or polled alarms, intelligent battery backup switching, battery reseal? function and 128 bytes of battery-backed user sram. backup battery current draw is less than 1.6a over the temperature range. the device is offered in a 20 ld soic module that cont ains the rtc and an embedded 32.768khz quartz crystal. the calib rated oscillator provides less than 5ppm drift over the full -40c to +85c temperature range. the rtc tracks time with separate registers for hours, minutes, and seconds. the calendar registers track date, month, year and day of the week and are accurate through 2099, with automatic leap year correction. daylight savings time adjustment is done automatically, using parameters entered by the user. power fail and battery monitors offer user-selectable trip levels. the time stamp function records the time and date of switchover from v dd to v bat power, and also from v bat to v dd power. the isl12022ma features enhanc ed immunity to esd per the iec61000-4-2 standard, and also provides improved resistance to system leakage related to environmental moisture. related literature ? see tb484 ?isl12022ma enhanced rtc module? ? see an1549 ?addressing power issues in real time clock applications? features ? embedded 32.768khz quartz crystal in the package ? 20 ld soic package (for dfn version, refer to the isl12020m) ?calendar ? on-chip oscillator temperature compensation ? 10-bit digital temperature sensor output ? 15 selectable frequency outputs ? interrupt for alarm or 15 selectable frequency outputs ? automatic backup to battery or supercapacitor ?v dd and battery status monitors ? battery reseal? function to extend battery shelf life ? power status brownout monitor ? time stamp for battery switchover ? 128 bytes battery-backed user sram ? 1.6a max battery current ?i 2 c bus? ? rohs compliant applications ? utility meters ? pos equipment ? printers and copiers ? digital cameras figure 1. typical application circuit gnd gnd gnd nc gnd gnd gnd nc nc nc nc nc v bat v dd gnd irq /f out nc nc scl sda isl12022ma 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 schottky diode bat54 battery 3.0v 3.3v c2 0.1f c1 0.1f r1 10k r2 10k r3 10k vdo scl sda gnd mcu interface irq /f out
isl12022ma fn7575 rev 5.00 page 2 of 31 september 5, 2012 block diagram pin configuration isl12022ma (20 ld soic) top view i 2 c interface control logic alarm frequency out rtc divider sda buffer crystal oscillator por switch scl buffer sda scl v dd v bat internal supply v trip seconds minutes hours day of week date month year user sram control registers gnd registers temperature sensor frequency control irq /f out + - gnd nc nc gnd nc nc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd nc nc v dd gnd gnd nc v bat gnd gnd nc irq /f out scl sda pin descriptions pin number symbol description 4, 5, 6, 9, 10, 15, 16, 17 nc no connection . do not connect to a signal or supply voltage. 7v bat backup supply . this input provides a backup supply voltage to the device. vbat supplies power to the device in the event that the vdd supply fails. this pin can be connected to a batter y, a supercapacitor or tied to ground if not used. see the battery monitor parameter in the ?? table on page 6. this pin should be tied to ground if not used. 11 sda serial data . sda is a bi-directional pin used to transfer data into and out of the device. it has an open drain output and may be or?ed with other open drain or open collector outputs. the input buffer is always active (not gated) in normal mode. an open drain output requires the use of a pull-up resistor. the output circuitry controls the fa ll time of the output signal with the use of a slope controlled pull-d own. the circuit is designed for 400khz i 2 c interface speeds. it is disabled when the backup power supply on the vbat pin is activated. 12 scl serial clock . the scl input is used to clock all serial data into and out of the device. the input buffer on this pin is always active (not gated). it is disabled when the backup power supply on the vbat pin is activated to minimize power consumption.
isl12022ma fn7575 rev 5.00 page 3 of 31 september 5, 2012 13 irq /f out interrupt output/frequency output (default 32.768khz frequency output) . this dual function pin can be used as an interrupt or frequency output pin. the irq /f out mode is selected via the frequency ou t control bits of the control/status register. interrupt mode . the pin provides an interrupt signal output. this signal notifies a host processor that an alarm has occurred and requests action. it is an open drain active low output. frequency output mode . the pin outputs a clock signal, which is related to the crystal frequency. the frequency output is user selectable and enabled via the i 2 c bus. it is an open drain output. the output is open drain and requires a pull-up resistor. 14 v dd power supply . chip power supply and ground pins. the device will operate with a power supply from v dd = 2.7v to 5.5vdc. a 0.1f capacitor is recommended on the vdd pin to ground. 1, 2, 3, 8, 18, 19, 20 gnd ground pin . pin descriptions (continued) pin number symbol description ordering information part number (notes 2, 3) part marking v dd range (v) temp range (c) package (rohs compliant) pkg. dwg. # ISL12022MAIBZ ISL12022MAIBZ 2.7 to 5.5 -40 to +85 20 ld soic m20.3 ISL12022MAIBZ-t (note 1) ISL12022MAIBZ 2.7 to 5. 5 -40 to +85 20 ld soic (tape and reel) m20.3 1. please refer to tb347 for details on reel specifications. 2. these intersil plastic packaged products employ special material sets, molding comp ounds and 100% matte tin plate plus anneal (e3) termination finish. these products do contain pb but th ey are rohs compliant by exemption 7 (pb in high melting temperature type solders, e lectronic ceramic parts (e.g. piezoelectronic devices)) and exemption 5 (pb in glas s of electronic components). th ese intersil rohs compliant pro ducts are compatible with both snpb and pb free soldering oper ations. these intersil rohs compliant produc ts are msl classified at pb-free peak refl ow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl12022ma . for more information on msl please see tech brief tb363 .
isl12022ma fn7575 rev 5.00 page 4 of 31 september 5, 2012 table of contents absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 dc operating characteristics rtc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 power-down timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 i 2 c interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 sda vs scl timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 symbol table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 typical performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 power control operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 normal mode (v dd ) to battery backup mode (v bat ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 battery backup mode (v bat ) to normal mode (v dd ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 power failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 battery level monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 real time clock operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 single event and interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 frequency output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 general purpose user sram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i 2 c serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 oscillator compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 real time clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 addresses [00h to 06h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 control and status registers (csr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 addresses [07h to 0fh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power supply control register (pwr_vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 battery voltage trip voltage register (pwr_vbat). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 initial at and dt setting register (itro). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 alpha register (alpha) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 beta register (beta) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 final analog trimming register (fatr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 final digital trimming register (fdtr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 alarm registers (10h to 15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 time stamp vdd to battery registers (tsv2b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 time stamp battery to vdd registers (tsb2v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 dst control registers (dstcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 temp registers (temp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 nppm registers (nppm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 xt0 registers (xt0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 alpha hot register (alphah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 user registers (accessed by using slave address 1010111x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 addresses [00h to 7fh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 protocol conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
isl12022ma fn7575 rev 5.00 page 5 of 31 september 5, 2012 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 application section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 power supply considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 battery backup details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 measuring oscillator accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 temperature compensation operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 daylight savings time (dst) example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 device handling precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
isl12022ma fn7575 rev 5.00 page 6 of 31 september 5, 2012 absolute maximum rating s thermal information voltage on v dd , v bat and irq /f out pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on scl and sda pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v esd rating human body model (per jesd22-a114f) . . . . . . . . . . . . . . . . . . . . . . >3kv machine model (per jesd22-a115b) . . . . . . . . . . . . . . . . . . . . . . . . >300v charge device model (per jesd22-c101d) . . . . . . . . . . . . . . . . . . . .2.2kv latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma shock resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 5000g, 0.3ms, 1/2 sine vibration (ultrasound cleaning not advised) . . . . . . . . . . . 20g/10-2000hz, thermal resistance (typical) ? ja (c/w) ? jc (c/w) 20 lead soic (notes 4, 5) . . . . . . . . . . . . . . 70 35 storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c pb-free reflow profile (note 6). . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for ? jc , the ?case temp? location is on top of the package and me asured in the center of the package between pins 6 and 15. 6. the isl12022ma oscillator initial accuracy can change after solder reflow attachment. the amount of change will depend on the reflow temperature and length of exposure. a general rule is to use only one reflow cycle and keep the temperature and time as short as possible. changes on the order of 1ppm to 3ppm can be expected with typical reflow profiles. dc operating characteristics rtc test conditions: vdd = +2.7 to +5.5v, ta = -40c to +85c, unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter conditions min (note 7) typ (note 8) max (note 7) units notes v dd main power supply (note 15) 2.7 5.5 v v bat battery supply voltage (note 15) 1.8 5.5 v9 i dd1 supply current. (i 2 cnotactive, temperature conversion not active, f out not active) v dd = 5v 4.1 15 a 10, 11 v dd = 3v 3.5 14 a 10, 11 i dd2 supply current. (i 2 c active, temperature conversion not active, f out not active) v dd = 5v 200 500 a 10, 11 i dd3 supply current. (i 2 cnotactive, temperature conversion active, f out not active) v dd = 5v 120 400 a 10, 11 i bat battery supply current v dd = 0v, v bat = 3v, t a = +25c 1.0 1.6 a 10 v dd = 0v, v bat = 3v 1.0 5.0 a 10 i batlkg battery input leakage v dd = 5.5v, v bat = 1.8v 100 na i li input leakage current on scl v il = 0v, v ih = v dd -1.0 0.1 1.0 a i lo i/o leakage current on sda v il = 0v, v ih = v dd -1.0 0.1 1.0 a v batm battery level monitor threshold -100 +100 mv v pbm brownout level monitor threshold -100 +100 mv v trip v bat mode threshold (note 15) 2.0 2.2 2.4 v v triphys v trip hysteresis 30 mv 13 v bathys v bat hysteresis 50 mv 13
isl12022ma fn7575 rev 5.00 page 7 of 31 september 5, 2012 oscillator accuracy ? fout i oscillator initial accuracy v dd ? 3.3v -2 +8 ppm 6, 17 ? fout r oscillator accuracy after reflow cycle v dd ? 3.3v 5 ppm 6, 17 ? fout t oscillator stability vs temperature v dd ? 3.3v 2 ppm 6, 18 ? fout v oscillator stability vs voltage 2.7v ? v dd ? 5.5v -3 +3 ppm 19 temp temperature sensor accuracy v dd = v bat = 3.3v 2 c 13 irq /f out (open drain output) v ol output low voltage v dd = 5v, i ol = 3ma 0.4 v v dd = 2.7v, i ol = 1ma 0.4 v dc operating characteristics rtc test conditions: vdd = +2.7 to +5.5v, ta = -40c to +85c, unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter conditions min (note 7) typ (note 8) max (note 7) units notes power-down timing test conditions: vdd = +2.7 to +5.5v, temperature = -40c to +85c, unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter conditions min (note 7) typ (note 8) max (note 7) units notes v ddsr- v dd negative slew rate 10 v/ms 12 v ddsr+ v dd positive slew rate, minimum 0.05 v/ms 16 i 2 c interface specifications test conditions: v dd = +2.7 to +5.5v, temperature = -40c to +85c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions min (note 7) typ (note 8) max (note 7) units notes v il sda and scl input buffer low voltage -0.3 0.3 x v dd v v ih sda and scl input buffer high voltage 0.7 x v dd v dd + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05 x v dd v 13, 14 v ol sda output buffer low voltage, sinking 3ma v dd = 5v, i ol = 3ma 0 0.02 0.4 v c pin sda and scl pin capacitance t a = +25c, f = 1mhz, v dd = 5v, v in =0v, v out = 0v 10 pf 13, 14 f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed. 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v dd , until sda exits the 30% to 70% of v dd window. 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v dd during a stop condition, to sda crossing 70% of v dd during the following start condition. 1300 ns t low clock low time measured at the 30% of v dd crossing. 1300 ns t high clock high time measured at the 70% of v dd crossing. 600 ns
isl12022ma fn7575 rev 5.00 page 8 of 31 september 5, 2012 t su:sta start condition setup time scl rising edge to sda falling edge. both crossing 70% of v dd . 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v dd to scl falling edge crossing 70% of v dd . 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v dd window, to scl rising edge crossing 30% of v dd. 100 ns t hd:dat input data hold time from scl falling edge crossing 30% of v dd to sda entering the 30% to 70% of v dd window. 20 900 ns t su:sto stop condition setup time from scl rising edge crossing 70% of v dd , to sda rising edge crossing 30% of v dd . 600 ns t hd:sto stop condition hold time from sda rising edge to scl falling edge. both crossing 70% of v dd . 600 ns t dh output data hold time from scl falling edge crossing 30% of v dd , until sda enters the 30% to 70% of v dd window. 0 ns t r sda and scl rise time from 30% to 70% of v dd. 20 + 0.1 x cb 300 ns 13, 14 t f sda and scl fall time from 70% to 30% of v dd. 20 + 0.1 x cb 300 ns 13, 14 cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf 13, 14 r pu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f . for cb = 400pf, max is about 2k ? ~2.5k ? . for cb = 40pf, max is about 15k ? ~20k ? 1 k ? 13, 14 notes: 7. parameters with min and/or max limits are 100% tested at +2 5c, unless otherwise specified. temperature limits established by characterization and are not production tested. 8. specified at +25c. 9. temperature conversion is inactive below v bat = 2.7v. device operation is not guaranteed at v bat <1.8v. 10. irq/ f out inactive. 11. v dd > v bat +v bathys 12. in order to ensure proper timekeeping, the v dd sr- specification must be followed. 13. limits should be considered typi cal and are not production tested. 14. these are i 2 c specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specificatio n. 15. minimum v dd and/or v bat of 1v to sustain the sram. the value is based on characterization and it is not tested. 16. to avoid eeprom recall issues, it is advised to use this minimum power up slew rate. not tested, shown as typical only. 17. defined as the deviation from a target oscillator frequency of 32,768.0hz at room temperature. 18. defined as the deviation from the room temperature measured 1hz frequency, v dd = 3.3v, at t a = -40c to +85c. 19. defined as the deviation at room temperature from the measured 1hz frequency (or equivalent) at v dd = 3.3, over the range of v dd = 2.7v to v dd =5.5v. i 2 c interface specifications test conditions: v dd = +2.7 to +5.5v, temperature = -40c to +85c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 7) typ (note 8) max (note 7) units notes
isl12022ma fn7575 rev 5.00 page 9 of 31 september 5, 2012 sda vs scl timing t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r figure 2. standard output lo ad for testing the device with v dd = 5.0v symbol table sda and irq /f out 1533 100pf 5.0v for v ol = 0.4v and i ol = 3ma equivalent ac output load circui t for v dd = 5v waveform inputs outputs must be steady will be steady ma y change from lo w to high will change from low to high ma y change from high to lo w will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance
isl12022ma fn7575 rev 5.00 page 10 of 31 september 5, 2012 typical performance curves temperature is +25c unless otherwise specified. figure 3. i bat vs v bat (v dd = 0v) figure 4. i bat vs temperature (v dd = 0v) figure 5. i dd1 vs temperature figure 6. i dd1 vs v dd figure 7. oscillator error vs temperature figure 8. f out vs i dd 800 850 900 950 1000 1050 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v bat voltage (v) v bat current (na) 600 800 1000 1200 1400 1600 -40-200 20406080 temperature (c) i bat (na) v bat = 1.8v v bat = 3.0v v bat = 5.5v 2 3 4 5 6 -40-200 20406080 temperature (c) i dd1 (a) vdd = 3.3v v dd = 2.7v v dd = 5.5v 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 2.7 3.2 3.7 4.2 4.7 5.2 v dd (v) i dd1 (a) -5 -4 -3 -2 -1 0 1 2 3 4 5 -40-200 20406080 temperature (c) f out frequency error (ppm) v dd = 2.7v v bat = 5.5v v dd = 3.3v 2 3 4 5 6 0.01 0.1 1 10 100 1k 10k 1m frequency output (hz) i dd (a) v dd = 2.7v v bat = 5.5v v dd = 3.3v
isl12022ma fn7575 rev 5.00 page 11 of 31 september 5, 2012 general description the isl12022ma device is a low power real time clock (rtc) with embedded temperature sensor and crystal. it contains crystal frequency compensation circuitry over the operating temperature range good to 5ppm accuracy. it also contains a clock/calendar with daylight savings time (dst ) adjustment, power fail and low battery monitors, brownout indicator, 1 periodic or polled alarm, intelligent battery backup switching and 128 bytes of battery- backed user sram. the oscillator uses an internal 32.768khz crystal. the real time clock tracks time with separate registers for hours, minutes and seconds. the device has calendar registers for date, month, year and day of the week. the calendar is accurate through 2099, with automatic leap year co rrection. in addition, the isl12022ma can be programmed fo r automatic daylight saving time (dst) adjustment by entering local dst information. the isl12022ma?s alarm can be set to any clock/calendar value for a match. for example, every minute, every tuesday or at 5:23 am on march 21. the alarm status is available by checking the status register, or the device can be configured to provide a hardware interrupt via the irq /f out pin. there is a repeat mode for the alarm allowing a periodic in terrupt every minute, every hour, every day, etc. the device also offers a backup power input pin. this vbat pin allows the device to be backed up by battery or supercapacitor with automatic switchover from v dd to v bat . the isl12022ma device is specified for v dd = 2.7v to 5.5v and the clock/calendar portion of the device remains fully operational in battery backup mode down to 1.8v (standby mode). the v bat level is monitored and reported against preselected levels. the first report is registered when the v bat level falls below 85% of nominal level; the second level is set for 75%. battery levels are stored in pwr_vbat registers. the isl12022ma offers a ?brownout? alarm once the v dd falls below a pre-selected trip level. this allows system micro to save vital information to memory before complete power loss. there are six v dd levels that could be sele cted for initiation of the brownout alarm. figure 9. i dd vs temperature, 3 different f out figure 10. i bat with tse = 1, btse = 1 vs temperature figure 11. i dd with tse = 1 vs temperature figure 12. osci llator change vs temp erature at different aging settings (iatr) (beta set for 1ppm steps) typical performance curves temperature is +25c unless otherwise specified. (continued) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40-200 20406080 temperature (c) supply current (a) f out = 32khz f out = 64hz f out = 1hz 20 30 40 50 60 70 80 90 100 110 -40-200 20406080 temperature (c) i bat (a) v dd = 1.8v v bat = 5.5v v dd = 3.0v 40 50 60 70 80 90 100 110 -40-200 20406080 temperature (c) i dd (a) v dd = 2.7v v bat = 5.5v v dd = 3.3v -80 -60 -40 -20 0 20 40 60 80 -40-200 20406080 temperature (c) frequency change (ppm) 62.5ppm 32ppm -31ppm -61.5ppm 0ppm
isl12022ma fn7575 rev 5.00 page 12 of 31 september 5, 2012 functional description power control operation the power control circuit accepts a v dd and a v bat input. many types of batteries can be used with intersil rtc products. for example, 3.0v or 3.6v lithium batteries are appropriate, and battery sizes are available that can power the isl12022ma for up to 10 years. another option is to use a supercapacitor for applications where v dd is interrupted for up to a month. see the ?application section? on page 27 for more information. normal mode (v dd ) to battery backup mode (v bat ) to transition from the v dd to v bat mode, both of the following conditions must be met: condition 1: v dd < v bat - v bathys where v bathys ? 50mv condition 2: v dd < v trip where v trip ? 2.2v battery backup mode (v bat ) to normal mode (v dd ) the isl12022ma device wi ll switch from the v bat to v dd mode when one of the following conditions occurs: condition 1: v dd > v bat + v bathys where v bathys ?? 50mv condition 2: v dd > v trip + v triphys where v triphys ? 30mv these power control situations are illustrated in figures 13 and 14. the i 2 c bus is deactivated in battery backup mode to reduce power consumption. aside from this, all rtc functions are operational during battery backup mode. except for scl and sda, all the inputs and outputs of the isl12022ma are active during battery backup mode unless disabled via the control register. the device time stamps the switchover from v dd to v bat and v bat to v dd , and the time is stored in t sv2b and t sb2v registers respectively. if multiple v dd power-down sequences occur before the status is read, the earliest v dd to v bat power-down time is stored and the most recent v bat to v dd time is stored. temperature conversion and compensation can be enabled in battery backup mode. bit btse in the beta register controls this operation, as described in ?beta register (beta)? on page 20. power failure detection the isl12022ma provides a real time clock failure bit (rtcf) to detect total power failure. it allows users to determine if the device has powered up after having lost all power to the device (both v dd and v bat ). brownout detection the isl12022ma monitors the v dd level continuously and provides warning if the v dd level drops below prescribed levels. there are six (6) levels that can be selected for the trip level. these values are 85% below popular v dd levels. the lvdd bit in the status register will be set to ?1? when brownout is detected. note that the i 2 c serial bus remains active unless the battery v trip levels are reached. battery level monitor the isl12022ma has a built-in warn ing feature once the backup battery level drops first to 85% and then to 75% of the battery?s nominal v bat level. when the battery voltage drops to between 85% and 75%, the lbat85 bit is se t in the status register. when the level drops below 75%, both lbat85 and lbat75 bits are set in the status register. the battery level monitor is not functional in battery backup mode. in order to read the monitor bits after powering up v dd , instigate a battery level measurement by setting the tse bit to "1" (beta register), and then read the bits. there is a battery time stamp fu nction available. once the v dd is low enough to enable switchover to the battery, the rtc time/date are written into the tsv2b register. this information can be read from the tsv2b registers to discover the point in time of the v dd power-down. if there are multip le power-down cycles before reading these registers, the first values stored in these registers will be retained. these registers will hold the original power-down value until they are cleared by setting clrts = 1 to clear the registers. v bat - v bathys v bat v bat + v bathys battery backup mode v dd v trip 2.2v 1.8v figure 13. battery switchover when v bat < v trip figure 14. battery switchover when v bat > v trip v trip v bat v trip + v triphys battery backup mode v dd v trip 3.0v 2.2v
isl12022ma fn7575 rev 5.00 page 13 of 31 september 5, 2012 the normal power switching of the isl12022ma is designed to switch into battery backup mode only if the v dd power is lost. this will ensure that the devi ce can accept a wide range of backup voltages from many ty pes of sources while reliably switching into backup mode. note that the isl12022ma is not guaranteed to operate with v bat < 1.8v. if the battery voltage is expected to drop lower than this minimum, correct operation of the device, (especially after a v dd power-down cycle) is not guaranteed. the minimum v bat to insure sram is stab le is 1.0v. below that, the sram may be corrupted when v dd power resumes. real time clock operation the real time clock (rtc) uses an integrated 32.768khz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, month, and year. the rtc also has leap-year correction. the clock also corrects for months having fewer than 31 days and has a bit that controls 24- hour or am/pm format. when the isl12022ma powers up after the loss of both v dd and v bat , the clock will not begin incrementing until at least one byte is written to the clock register. single event and interrupt the alarm mode is enabled via the msb bit. choosing single event or interrupt alarm mode is selected via the im bit. note that when the frequency output function is enabled, the alarm function is disabled. the standard alarm allows for alarms of time, date, day of the week, month, and year. when a time alarm occurs in single event mode, the irq /f out pin will be pulled low and the alarm status bit (alm) will be set to ?1?. the pulsed interrupt mode allows for repetitive or recurring alarm functionality. hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. thus, it will alarm as often as every minute (if only the nth second is set) or as infreq uently as once a year (if at least the nth month is set). during pulsed interrupt mode, the irq /f out pin will be pulled low for 250ms and the alarm status bit (alm) will be set to ?1?. the alm bit can be reset by the user or cleared automatically using the auto reset mode (see ar st bit). the alarm function can be enabled/disabled during ba ttery backup mode using the fobatb bit. for more information on the alarm, please see ?alarm registers (10h to 15h)? on page 21. frequency output mode the isl12022ma has the option to provide a clock output signal using the irq /f out open drain output pin. the frequency output mode is set by using the fo bits to select 15 possible output frequency values from 1/32hz to 32khz. the frequency output can be enabled/disabled during battery backup mode using the fobatb bit. general purpose user sram the isl12022ma provides 128 bytes of user sram. the sram will continue to operate in battery backup mode. however, it should be noted that the i 2 c bus is disabled in battery backup mode. i 2 c serial interface the isl12022ma has an i 2 c serial bus interface that provides access to the control and status registers and the user sram. the i 2 c serial interface is compatible with other industry i 2 c serial bus protocols using a bi-directional data signal (sda) and a clock signal (scl). oscillator compensation the isl12022ma provides both initial timing correction and temperature correction due to vari ation of the crystal oscillator. analog and digital trimming control is provided for initial adjustment, and a temperature compensation function is provided to automatically correct for temperat ure drift of the crystal. initial values for the initial at and dt settings (itr0), temperature coefficient (alpha), crystal capacitance (beta), as well as the crystal turn-over temperature (xto ), are preset internally and recalled to ram registers on power-up. the compensation function can be enabled/disabled at any time and can be used in battery mode as well. register descriptions the battery-backed registers are accessible following a slave byte of ?1101111x? and reads or wr ites to addresses [00h:2fh]. the defined addresses and defaul t values are described in the table 1. the battery backed general purpose sram has a different slave address (1010111x), so it is not possible to read/write that section of memo ry while accessing the registers. register access the contents of the registers can be modified by performing a byte or a page write operation directly to any register address. the registers are divided into 8 sections. they are: 1. real time clock (7 bytes): address 00h to 06h. 2. control and status (9 bytes): address 07h to 0fh. 3. alarm (6 bytes): address 10h to 15h. 4. time stamp for battery status (5 bytes): address 16h to 1ah. 5. time stamp for v dd status (5 bytes): address 1bh to 1fh. 6. day light saving time (8 bytes): 20h to 27h. 7. temp (2 bytes): 28h to 29h. 8. crystal net ppm correction, nppm (2 bytes): 2ah, 2bh. 9. crystal turnover temperature, xt0 (1 byte): 2ch. 10. crystal alpha at high temp erature, alpha_h (1 byte): 2dh. 11. scratch pad (2 bytes): address 2eh and 2fh. write capability is allowable into the rtc registers (00h to 06h) only when the wrtc bit (bit 6 of address 08h) is set to ?1?. a multi-byte read or write operation should be limited to one section per operation for best rtc time keeping performance. a register can be read by perf orming a random read at any address at any time. this returns the contents of that register location. additional registers are read by performi ng a sequential read. for the rtc and alarm regi sters, the read instruction latches all clock registers into a buffer, so an update of the clock
isl12022ma fn7575 rev 5.00 page 14 of 31 september 5, 2012 does not change the time being read. at the end of a read, the master supplies a stop condition to end the operation and free the bus. after a read, the addr ess remains at the previous address +1 so the user can execute a current address read and continue reading the next register . when the previous address is 2fh, the next address will wrap around to 00h. it is not necessary to set the wrtc bit prior to writing into the control and status, alarm, and user sram registers. table 1. register memory map (yellow shading indicates read-only bits) addr. section reg name bit range default 76543210 00h rtc sc 0 sc22 sc21 sc20 sc13 sc12 sc11 sc10 0 to 59 00h 01h mn 0 mn22 mn21 mn20 mn13 mn12 mn11 mn10 0 to 59 00h 02h hr mil 0 hr21 hr20 hr13 hr12 hr11 hr10 0 to 23 00h 03h dt 0 0 dt21 dt20 dt13 dt12 dt11 dt10 1 to 31 01h 04h mo 0 0 0 mo20 mo13 mo12 mo11 mo10 1 to 12 01h 05h yr yr23 yr22 yr21 yr20 yr13 yr12 yr11 yr10 0 to 99 00h 06h dw 0 0 0 0 0 dw2 dw1 dw0 0 to 6 00h 07h csr sr busy oscf dstadj alm lvdd lbat85 lbat75 rtcf n/a 01h 08h int arst wrtc im fobatb fo3 fo2 fo1 fo0 n/a 01h 09h pwr_vd d clrtsddddv dd trip2 v dd trip1 v dd trip0 n/a 00h 0ah pwr_vba t dreseal b vb85tp2 vb85tp1 vb85tp0 vb75tp2 vb75tp1 vb75tp0 n/a 00h 0bh itro idtr0 1 idtr00 iatr05 iatr04 iatr03 iatr02 iatr01 iatr00 n/a xxh 0ch alpha d alpha6 alpha5 alpha4 alpha3 alpha2 alpha1 alpha0 n/a xxh 0dh beta tse btse btsr beta4 beta3 beta2 beta1 beta0 n/a xxh 0eh fatr 0 0 ffatr5 fatr4 fatr3 fatr2 fatr1 fatr0 n/a 00h 0fh fdtr 0 0 0 fdtr4 fdtr3 fdtr2 fdtr1 fdtr0 n/a 00h 10h alarm sca0 esca0 sca022 sca021 sca020 sca013 sca012 sca011 sca010 00 to 59 00h 11h mna0 emna 0 mna022 mna021 mna020 mna013 mn a012 mna011 mna010 00 to 59 00h 12h hra0 ehra0 d hra021 hra020 hra013 hra012 hra011 hra010 0 to 23 00h 13h dta0 edta0 d dta021 dta020 dta013 dta012 dta011 dta010 01 to 31 00h 14h moa0 emoa0 0 d d moa020 moa013 moa012 moa011 moa010 01 to 12 00h 15h dwa0 edwa 0 d d d d dwa02 dwa01 dwa00 0 to 6 00h 16h tsv2b vsc 0 vsc22 vsc21 vsc20 vsc13 vsc12 vsc11 vsc10 0 to 59 00h 17h vmn 0 vmn22 vmn21 vmn20 vmn13 vmn12 vmn11 vmn10 0 to 59 00h 18h vhr vmil 0 vhr21 vhr20 vhr13 vhr12 vhr11 vhr10 0 to 23 00h 19h vdt 0 0 vdt21 vdt20 vdt13 vdt12 vdt11 vdt10 1 to 31 00h 1ah vmo 0 0 0 vmo20 vmo13 vmo12 vmo11 vmo10 1 to 12 00h
isl12022ma fn7575 rev 5.00 page 15 of 31 september 5, 2012 real time clock registers addresses [00h to 06h] rtc registers (sc, mn, hr, dt, mo, yr, dw) these registers depict bcd representations of the time. as such, sc (seconds) and mn (minutes) range from 0 to 59, hr (hour) can either be a 12-hour or 24-hour mode, dt (date) is 1 to 31, mo (month) is 1 to 12, yr (year) is 0 to 99, and dw (day of the week) is 0 to 6. the dw register provides a day of the week status and uses three bits (dw2 to dw0) to represent the seven days of the week. the counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-? the assignment of a numerical value to a specific day of the week is arbitrary and may be de cided by the system software designer. the default value is defined as ?0?. 24-hour time if the mil bit of the hr register is ?1?, the rtc uses a 24-hour format. if the mil bit is ?0?, the rtc uses a 12-hour format and hr21 bit functions as an am/pm indicator with a ?1? representing pm. the clock defaults to 12-hour format time with hr21 = ?0?. leap years leap years add the day february 29 and are defined as those years that are divisible by 4. years divi sible by 100 are not leap years, unless they are also divisible by 400. this means that the year 2000 is a leap year and the year 2100 is not. the isl12022ma does not correct for the leap year in the year 2100. 1bh tsb2v bsc 0 bsc22 bsc21 bsc20 bsc13 bsc12 bsc11 bsc10 0 to 59 00h 1ch bmn 0 bmn22 bmn21 bmn20 bmn13 bmn12 bmn11 bmn10 0 to 59 00h 1dh bhr bmil 0 bhr21 bhr20 bhr13 bhr12 bhr11 bhr10 0 to 23 00h 1eh bdt 0 0 bdt21 bdt20 bdt13 bdt12 bdt11 bdt10 1 to 31 00h 1fh bmo 0 0 0 bmo20 bmo13 bmo12 bmo11 bmo10 1 to 12 00h 20h dstcr dstmofd dste d d dstmofd 20 dstmofd 13 dstmofd 12 dstmofd 11 dstmofd 10 1 to 12 00h 21h dstdwfd d dstdwfd e dstwkfd 12 dstwkfd 11 dstwkfd 10 dstdwfd 12 dstdwfd 11 dstdwfd 10 0 to 6 00h 22h dstdtfd d d dstdtfd2 1 dstdtfd2 0 dstdtfd1 3 dstdtfd1 2 dstdtfd1 1 dstdtfd1 0 1 to 31 00h 23h dsthrfd d d dsthrfd2 1 dsthrfd2 0 dsthrfd1 3 dsthrfd1 2 dsthrfd1 1 dsthrfd1 0 0 to 23 00h 24h dstmorv d d d dstmorv 20 dstmorv 13 dstmor1 2v dstmorv 11 dstmorv 10 01 to 12 00h 25h dstdwrv d dstdwr ve dstwkrv1 2 dstwkrv 11 dstwkrv 10 dstdwrv 12 dstdwrv 11 dstdwrv 10 0 to 6 00h 26h dstdtrv d d dstdtrv2 1 dstdtrv2 0 dstdtrv1 3 dstdtrv1 2 dstdtrv1 1 dstdtrv1 0 01 to 31 00h 27h dsthrrv d d dsthrrv2 1 dsthrrv2 0 dsthrrv1 3 dsthrrv1 2 dsthrrv1 1 dsthrrv1 0 0 to 23 00h 28h temp tk0l tk07 tk06 tk05 tk04 tk03 tk02 tk01 tk00 00 to ff 00h 29h tk0m 0 0 0 0 0 0 tk09 tk08 00 to 03 00h 2ah nppm nppml nppm 7 nppm6 nppm5 nppm4 nppm3 nppm2 nppm1 nppm0 00 to ff 00h 2bh nppmh 0 0 0 0 0 nppm10 nppm9 nppm8 00 to 07 00h 2ch xt0 xt0 d d d xt4 xt3 xt2 xt1 xt0 00 to ff xxh 2dh alphah alphah d alp_h6 alp_h5 alp_h4 alp_h3 alp_h2 alp_h1 alp_h0 00 to 7f xxh 2eh gpm gpm1 gpm17 gpm16 gpm15 gpm14 gpm13 gpm12 gpm11 gpm10 00 to ff 00h 2fh gpm2 gpm2 7 gpm26 gpm25 gpm24 gpm23 gpm22 gpm21 gpm20 00 to ff 00h table 1. register memory map (yellow shad ing indicates read-only bits) (continued) addr. section reg name bit range default 76543210
isl12022ma fn7575 rev 5.00 page 16 of 31 september 5, 2012 control and status registers (csr) addresses [07h to 0fh] the control and status registers consist of the status register, interrupt and alarm register, analog trimming and digital trimming registers. status register (sr) the status register is located in the memory map at address 07h. this is a volatile register that provides either control or status of rtc failure (rtcf), battery level monitor (lbat85, lbat75), alarm trigger, daylight saving time, crystal oscillator enable and temperature conversion in progress bit. busy bit (busy) busy bit indicates temperature se nsing is in progress. in this mode, alpha, beta and itro registers are disabled and cannot be accessed. oscillator fail bit (oscf) oscillator fail bit indicates that the oscillator has failed. the oscillator frequency is either ze ro or very far from the desired 32.768khz due to failure, pc board contamination or mechanical issues. daylight saving time change bit (dstadj) dstadj is the daylight saving time adjusted bit. it indicates the daylight saving time forward adjustment has happened. if a dst forward event happens, dstadj will be set to ?1?. the dstadj bit will stay high when dstfd event ha ppens, and will be reset to ?0? when the dst reverse event happens. it is read-only and cannot be written. setting time during a dst fo rward period will not set this bit to ?1?. the dste bit must be enabled when the rtc time is more than one hour before the dst forward or dst reverse event time setting, or the dst event correction will not happen. dstadj is reset to ?0? upon power-up. it will reset to ?0? when the dste bit in register 15h is set to ?0? (dst disabled ), but no time adjustment will happen. alarm bit (alm) this bit announces if the alarm matches the real time clock. if there is a match, the respective bit is set to ?1?. this bit can be manually reset to ?0? by the user or automatically reset by enabling the auto-reset bit (see arst bit). a write to this bit in the sr can only set it to ?0?, not ?1?. an alarm bit that is set by an alarm occurring during an sr read operation will remain set after the read operation is complete. low v dd indicator bit (lv dd ) this bit indicates when v dd has dropped below the pre-selected trip level (brownout mode). the trip points for the brownout levels are selected by three bits: vdd trip2, vdd trip1 and vdd trip0 in pwr_ vdd registers. the lvdd detection is only enabled in vdd mode and the detection happens in real time. the lvdd bit is set whenever the v dd has dropped below the pre-selected trip level, and self clears whenever the v dd is above the pre-selected trip level. low battery indicator 85% bit (lbat85) in normal mode (v dd ), this bit indicates when the battery level has dropped below the pre-selected trip levels. the trip points are selected by three bits: vb85tp2, vb85tp1 and vb85tp0 in the pwr_vbat registers. the lbat85 detection happens automatically once every minute when seconds register reaches 59. the detection can also be manually triggered by setting the tse bit in beta register to ?1?. the lbat85 bit is set when the v bat has dropped below the pre-selected trip level, and will self clear when the v bat is above the pre-selected trip level at the next detection cycle either by manual or automatic trigger. in battery mode (v bat ), this bit indicates the device has entered into battery mode by polling once every 10 minutes. the lbat85 detection happens automatically once when the minute register reaches x9h or x0h minutes. example - when the lbat85 is set to ?1? in battery mode the minute the register changes to 19h when the device is in battery mode, the lbat85 is set to ?1? the next time the device switches back to normal mode. example - when the lbat85 remains at ?0? in battery mode if the device enters into battery mode after the minute register reaches 20h and switches back to normal mode before the minute register reaches 29h, then the lbat85 bit will remain at ?0? the next time the device switches back to normal mode. low battery indicator 75% bit (lbat75) in normal mode (v dd ), this bit indicates when the battery level has dropped below the pre-selected trip levels. the trip points are selected by three bits: vb75tp2, vb75tp1 and vb75tp0 in the pwr_vbat registers. the lbat75 detection happens automatically once every minute when seconds register reaches 59. the detection can also be manually triggered by setting the tse bit in beta register to ?1?. the lbat75 bit is set when the v bat has dropped below the pre-selected trip level, and will self clear when the v bat is above the pre-selected trip level at the next detection cycle either by manual or automatic trigger. in battery mode (v bat ), this bit indicates the device has entered into battery mode by polling once every 10 minutes. the lbat85 detection happens automatically once when the minute register reaches x9h or x0h minutes. example - when the lbat75 is set to ?1? in battery mode the minute register changes to 30h when the device is in battery mode, the lbat75 is set to ?1? th e next time the device switches back to normal mode. example - when the lbat75 remains at ?0? in battery mode if the device enters into battery mode after the minute register reaches 49h and switches back to normal mode before minute table 2. status register (sr) addr 7 6 5 4 3 2 1 0 07h busy oscf dstdj alm lvdd lbat85 lbat75 rtcf
isl12022ma fn7575 rev 5.00 page 17 of 31 september 5, 2012 register reaches 50h, then the lb at75 bit will remain at ?0? the next time the device switches back to normal mode. real time clock fail bit (rtcf) this bit is set to a ?1? after a total power failure. this is a read only bit that is set by hardware (isl12022ma internally) when the device powers up after having lost all power (defined as v dd = 0v and v bat = 0v). the bit is set regardless of whether v dd or v bat is applied first. the loss of only one of the supplies does not set the rtcf bit to ?1?. the first valid write to the rtc section after a complete power failure resets the rtcf bit to ?0? (writing one byte is sufficient). interrupt control register (int) automatic reset bit (arst) this bit enables/disables the automatic reset of the alm, lvdd, lbat85, and lbat75 status bits only. when arst bit is set to ?1?, these status bits are reset to ?0? after a valid read of the respective status register (with a valid stop condition). when the arst is cleared to ?0?, the user must manually reset the alm, lvdd, lbat85, and lbat75 bits. write rtc enable bit (wrtc) the wrtc bit enables or disables write capability into the rtc timing registers. the factory defa ult setting of this bit is ?0?. upon initialization or power-up, the wrtc must be set to ?1? to enable the rtc. upon the completion of a valid write (stop), the rtc starts counting. the rtc intern al 1hz signal is synchronized to the stop condition during a valid write cycle. interrupt/alarm mode bit (im) this bit enables/disables the interrupt mode of the alarm function. when the im bit is set to ?1?, the alarm will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the irq /f out pin when the rtc is triggered by the alarm, as defined by the alarm registers (0ch to 11h). when the im bit is cleared to ?0?, the alar m will operate in standard mode, where the irq /f out pin will be set low until the alm status bit is cleared to ?0?. frequency output and interrupt bit (fobatb) this bit enables/disables the irq /f out pin during battery backup mode (i.e. v bat power source active). when the fobatb is set to ?1?, the irq /f out pin is disabled during battery backup mode. this means that both the frequency output and alarm output functions are disabled. when the fobatb is cleared to ?0?, the irq /f out pin is enabled during battery backup mode. note that the open drain irq /f out pin will need a pull-up to the battery voltage to operate in battery backup mode. frequency out control bits (fo <3:0>) these bits enable/disable the frequency output function and select the output frequency at the irq /f out pin. see table 5 for frequency selection. default for the isl12022ma is fo<3:0> = 1h, or 32.768khz output (f out is on ). when the frequency mode is enabled, it will override the alarm mode at the irq /f out pin. power supply control register (pwr_vdd) clear time stamp bit (clrts) this bit clears time stamp v dd to battery (tsv2b) and time stamp battery to v dd registers (tsb2v). the default setting is 0 (clrts = 0) and the enabled setting is 1 (clrts = 1). v dd brownout trip voltage bits (v dd trip<2:0>) these bits set the trip level for the v dd alarm, indicating that v dd has dropped below a preset level. in this event, the lvdd bit in the status register is set to ?1?. see table 7. table 3. interrupt control register (int) addr 7 6 5 4 3210 08h arst wrtc im fobatb fo3 fo2 fo1 fo0 table 4. im bit interrupt/alarm frequency 0 single time event set by alarm 1 repetitive/recurring time event set by alarm table 5. frequency selection of irq /f out pin frequencyf ou t units fo3 fo2 fo1 fo0 0hz0000 32768 hz 0 0 0 1 4096 hz 0 0 1 0 1024 hz 0 0 1 1 64 hz 0 1 0 0 32 hz 0 1 0 1 16 hz 0 1 1 0 8hz0111 4hz1000 2hz1001 1hz1010 1/2 hz 1 0 1 1 1/4 hz 1 1 0 0 1/8 hz 1 1 0 1 1/16 hz 1 1 1 0 1/32 hz 1 1 1 1 table 6. addr 7 6 5 4 3 2 1 0 09h clrts 0 0 0 0 v dd trip2 v dd trip1 v dd trip0
isl12022ma fn7575 rev 5.00 page 18 of 31 september 5, 2012 battery voltage trip voltage register (pwr_vbat) this register controls the trip points for the two v bat alarms, with levels set to approximately 85% and 75% of the nominal battery level. reseal bit (resealb) this is the reseal bit for actively disconnecting the v bat pin from the internal circuitry. setting this bit allows the device to disconnect the battery and eliminate standby current drain while the device is unused. once v dd is powered up, this bit is reset and the v bat pin is then connected to the internal circuitry. the application for this bit involves placing the chip on a board with a battery and testing the bo ard. once the board is tested and ready to ship, it is desirable to disconnect the battery to keep it fresh until the board or unit is placed into final use. setting resealb = ?1? initiates the battery disconnect, and after vdd power is cycled down and up again, the reseal bit is cleared to ?0?. battery level monitor trip bits (vb85tp <2:0>) three bits select the first alarm (85% of nominal v bat ) level for the battery voltage monitor. there are total of 7 levels that could be selected for the first alarm. any of the of levels could be selected as the first alarm with no reference as to nominal battery voltage level. see table 9. battery level monitor trip bits (vb75tp <2:0>) three bits select the second alarm (75% of nominal v bat ) level for the battery voltage monitor. there are total of 7 levels that could be selected for the second alarm. any of the of levels could be selected as the second alarm with no refere nce as to nominal battery voltage level. see table 10. initial at and dt setting register (itro) these bits are used to trim the initial error (at room temperature) of the crystal. both digital trim ming (dt) and analog trimming (at) methods are available. the digital trimming uses clock pulse skipping and insertion for fr equency adjustment. analog trimming uses load capacitance adjustment to pull the oscillator frequency. a range of +62.5ppm to -61.5ppm is possible with combined digital and analog trimming. initial values for the itr0 register are preset internally and recalled to ram registers on power-up. these values are pre-set in device production and are read-only. they cannot be overwritten by the user. if an a pplication requires adjustment of the iatr bits outside the preset values, the user should contact intersil . aging and initial trim digital trimming bits (idtr0<1:0>) these bits allow 30.5ppm initial trimming ra nge for the crystal frequency. this is meant to be a coarse adjustment if the range needed is outside that of the iatr control. see table 11. the idtr0 register should only be changed while the tse (temp sense enable) bit is ?0?. the isl12022ma has a preset in itial digital trimming value corresponding to the crystal in the module. this value is recalled on initial power-up and is read-only. it cannot be overwritten by the user. table 7. v dd trip levels v dd trip2 v dd trip1 v dd trip0 trip voltage (v) 0 0 0 2.295 0 0 1 2.550 0 1 0 2.805 0 1 1 3.060 1 0 0 4.250 1 0 1 4.675 table 8. addr 7 6 5 4 3 2 1 0 0ah d resealb vb85 tp2 vb85 tp1 vb85 tp0 vb75 tp2 vb75t p1 vb75 tp0 table 9. vb85t alarm level vb85tp2 vb85tp1 vb85tp0 battery alarm trip level (v) 000 2.125 0 0 1 2.295 0 1 0 2.550 0 1 1 2.805 1 0 0 3.060 1 0 1 4.250 1 1 0 4.675 table 10. battery level monito r trip bits (vb75tp <2:0>) vb75tp2 vb75tp1 vb75tp0 battery alarm trip level (v) 000 1.875 0 0 1 2.025 0 1 0 2.250 011 2.475 1 0 0 2.700 1 0 1 3.750 110 4.125 table 11. idtr0 trimming range idtr01 idtr00 trimming range 00default/disabled 0 1 +30.5ppm 100ppm 1 1 -30.5ppm
isl12022ma fn7575 rev 5.00 page 19 of 31 september 5, 2012 aging and initial analog trimming bits (iatr0<5:0>) the initial analog trimming register allows +32ppm to -31ppm adjustment in 1ppm/bit increments. this enables fine frequency adjustment for trimming initial crystal accuracy error or to correct for aging drift. the isl12022ma has a preset initial analog trimming value corresponding to the crystal in the module. this value is recalled on initial power-up, is preset in device production and is read-only. it cannot be overwritten by the user. alpha register (alpha) the alpha variable is 8 bits and is defined as the temperature coefficient of crystal from -40c to t0, or the alpha cold (there is an alpha hot register that must be programmed as well). it is normally given in units of ppm/c 2 , with a typical value of -0.034. the isl12022ma device uses a scaled version of the absolute value of this coefficient in order to get an integer value. therefore, alpha <7:0> is defined as the (|actual alpha value| x 2048) and converted to binary. for example, a crystal with alpha of - 0.034ppm/c 2 is first scaled (|2048*(-0.034)| = 70d) and then converted to a binary number of 01000110b. the practical range of actual alpha values is from -0.020 to -0.060. the isl12022ma has a preset alpha value corresponding to the crystal in the module. this value is recalled on initial power-up and is preset in device production. it is read only and cannot be overwritten by the user. table 12. initial at and dt setting register addr 7 6 5 4 3 2 1 0 0bh idtr01 idtr00 iatr0 5 iatr0 4 iatr03 iatr0 2 iatr0 1 iatr0 0 table 13. iatro trimming range iatr05 iatr04 iatr03 iatr02 iatr01 iatr00 trimming range 000000 +32 000001 +31 000010 +30 000011 +29 000100 +28 000101 +27 000110 +26 000111 +25 001000 +24 001001 +23 001010 +22 001011 +21 001100 +20 001101 +19 001110 +18 001111 +17 010000 +16 010001 +15 010010 +14 010011 +13 010100 +12 010101 +11 010110 +10 010111 +9 011000 +8 011001 +7 011010 +6 011011 +5 011100 +4 011101 +3 011110 +2 011111 +1 100000 0 100001 -1 100010 -2 100011 -3 100100 -4 100101 -5 100110 -6 100111 -7 101000 -8 101001 -9 101010 -10 101011 -11 101100 -12 101101 -13 101110 -14 101111 -15 110000 -16 110001 -17 110010 -18 110011 -19 110100 -20 110101 -21 110110 -22 110111 -23 111000 -24 111001 -25 111010 -26 111011 -27 111100 -28 111101 -29 111110 -30 111111 -31 table 14. alpha register addr76543210 0ch d alpha 6 alpha 5 alpha 4 alpha 3 alpha 2 alpha 1 alpha 0 table 13. iatro trimming range (continued) iatr05 iatr04 iatr03 iatr02 iatr01 iatr00 trimming range
isl12022ma fn7575 rev 5.00 page 20 of 31 september 5, 2012 beta register (beta) the beta register has special write properties. only the tse, btse and btsr bits can be writte n; the beta bits are read-only. a write to both bytes in this register will only change the 3 msb?s (tse, btse, btsr), and the 5 lsb?s will remain the same as set at the factory. temperature sensor enabled bit (tse) this bit enables the temperature sensing operation, including the temperature sensor, a/d converter and fatr/fdtr register adjustment. the default mode after power-up is disabled: (tse = 0). to enable the operation, tse should be set to 1. (tse = 1). when temp sense is disabled, the initial values for iatr and idtr registers are used for frequency control. when tse is set to 1, the temperature conversion cycle begins and will end when two temperature conversions are completed. the average of the two conversions is in the temp registers. temp sensor conversion in battery mode bit (btse) this bit enables the temperature sensing and correction in battery mode. btse = 0 (default) no conversion, temp sensing or compensation in battery mode. btse = 1 indicates temp sensing and compensation enabled in batt ery mode. the btse is disabled when the battery voltage is lower than 2.7v. no temperature compensation will take place with vbat<2.7v. frequency of temperature sensing and correction bit (btsr) this bit controls the frequency of temp sensing and correction. btsr = 0 default mode is every 10 minutes, btsr = 1 is every 1.0 minute. note that btse has to be enabled in both cases. see table 16. the temperature measurement conv ersion time is the same for battery mode as for v dd mode, approximately 22ms. the battery mode current will increase during this conversion time to typically 68a. the average increase in battery current is much lower than this due to the small duty cycle of the on-time versus off-time for the conversion. to figure the average increase in battery current, we take the change in current times the duty cycle. for the 1 minute temperature period, the average current is expressed in equation 1: for the 10 minute temperature period the average current is expressed in equation 2: if the application has a stable temperature environment that doesn?t change quickly, the 10 minu te option will work well and the backup battery lifetime impact is minimized. if quick temperature variations are expected (multiple cycles of more than 10 within an hour), then the 1 minute option should be considered and the slightly higher battery current figured into overall battery life. gain factor of at bit (beta<4:0>) beta is specified to take care of the cm variations of the crystal. most crystals specify cm around 2.2ff. for example, if cm > 2.2ff, the actual at steps may reduce from 1ppm/step to approximately 0.80ppm/step. beta is then used to adjust for this variation and restore the step size to 1ppm/step. beta values are limited in the range from 01000 to 11111, as shown in table 17 . to use table 17, the device is tested at two at settings as follows: beta values = (at(max) - at (min))/63, where: at(max) = f out in ppm (at at = 00h) and at(min) = f out in ppm (at at = 3fh). the beta values result is indexed in the right hand column and the resulting beta factor (for the register) is in the same row in the left column. the isl12022ma has a preset beta value corresponding to the crystal in the module. this value is recalled on initial power-up and is preset in device production. it is read only and cannot be overwritten by the user. table 15. addr76543210 0dh tse btse btsr beta4 beta3 beta2 beta1 beta0 table 16. frequency of temperature sensing and correction bit btse btsr tc period in battery mode 00off 01off 1010 minutes 111 minute table 17. beta values beta<4:0> at step adjustment 01000 0.5000 00111 0.5625 00110 0.6250 00101 0.6875 00100 0.7500 00011 0.8125 00010 0.8750 00001 0.9375 00000 1.0000 10000 1.0625 10001 1.1250 10010 1.1875 ? i bat 0.022s 60s ----------------- - = 68 ? a 250na = ? (eq. 1) ? i bat 0.022s 600s ----------------- - = 68 ? a 25na = ? (eq. 2)
isl12022ma fn7575 rev 5.00 page 21 of 31 september 5, 2012 final analog trimming register (fatr) this register shows the final setting of at after temperature correction. it is read-only; the user cannot overwrite a value to this register. this value is accessibl e as a means of monitoring the temperature compensation function. see table 18 and table 19 (for values). final digital trimming register (fdtr) this register shows the final setting of dt after temperature correction. it is read-only; the user cannot overwrite a value to this register. the value is acce ssible as a means of monitoring the temperature compensation function. the corresponding clock adjustment values are shown in table 20. the fdtr setting has both positive and negative settings to adjust for any offset in the crystal.. alarm registers (10h to 15h) the alarm register bytes are set up identical to the rtc register bytes, except that the msb of each byte functions as an enable bit (enable = ?1?). these enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. note that there is no alarm byte for year. the alarm function works as a comparison between the alarm registers and the rtc registers. as the rtc advances, the alarm will be triggered once a match occurs between the alarm registers and the rtc registers. any one alarm register, multiple registers, or all registers can be enabled for a match. there are two alarm operation mo des: single event and periodic interrupt mode: ? single event mode is enabled by setting the bit 7 on any of the alarm registers (esca0... edwa0) to ?1?, the im bit to ?0?, and disabling the frequency output. this mode permits a one-time match between the alarm registers and the rtc registers. once this match occurs, the alm bit is set to ?1? and the irq /f out output will be pulled low and will remain low until the alm bit is reset. this can be done manually or by using the auto-reset feature. ? interrupt mode is enabled by setting the bit 7 on any of the alarm registers (esca0... edwa0) to ?1?, the im bit to ?1?, and disabling the frequency output. the irq /f out output will now be pulsed each time an alarm occurs. this means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. this mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. 10011 1.2500 10100 1.3125 10101 1.3750 10110 1.4375 10111 1.5000 11000 1.5625 11001 1.6250 11010 1.6875 11011 1.7500 11100 1.8125 11101 1.8750 11110 1.9375 11111 2.0000 table 18. final analog trimming register addr76543210 0eh 0 0 fatr5 fatr4 fatr3 fatr2 fatr1 fatr0 table 19. final digital trimming register addr765 4 3 2 1 0 0fh 0 0 0 fdtr4 fdtr3 fdtr2 fdtr1 fdtr0 table 20. clock adjustment values for final digital trimming register fdtr<4:0> decimal ppm adjustment 00000 0 0 00001 1 30.5 00010 2 61 00011 3 91.5 00100 4 122 00101 5 152.5 table 17. beta values (continued) beta<4:0> at step adjustment 00110 6 183 00111 7 213.5 01000 8 244 01001 9 274.5 01010 10 305 10000 0 0 10001 -1 -30.5 10010 -2 -61 10011 -3 -91.5 10100 -4 -122 10101 -5 -152.5 10110 -6 -183 10111 -7 -213.5 11000 -8 -244 11001 -9 -274.5 11010 -10 -305 table 20. clock adjustment values for final digital trimming register (continued) fdtr<4:0> decimal ppm adjustment
isl12022ma fn7575 rev 5.00 page 22 of 31 september 5, 2012 to clear a single event alarm, th e alm bit in the status register must be set to ?0? with a write. note that if the arst bit is set to 1 (address 08h, bit 7), the alm bit will automatically be cleared when the status register is read. following are examples of both single event and periodic interrupt mode alarms. example 1 ? alarm set with single interrupt (im = ?0?) ? a single alarm will occur on january 1 at 11:30 a.m. ? set alarm registers as follows: after these registers are set, an alarm will be generated when the rtc advances to exactly 11:30 a. m. on january 1 (after seconds changes from 59 to 00) by setting the alm bit in the status register to ?1? and also bringing the irq /f out output low. example 2 ? pulsed interrupt once per minute (im = ?1?) ? interrupts at one minute interval s when the seconds register is at 30 seconds. ? set alarm registers as follows: once the registers are set, the following waveform will be seen at irq /f out : note that the status register al m bit will be set each time the alarm is triggered, but does not need to be read or cleared. time stamp v dd to battery registers (tsv2b) the tsv2b register bytes are identical to the rtc register bytes, except they do not extend beyond the month. the time stamp captures the first v dd to battery voltage transition time, and will not update upon subsequent events until cleared (only the first event is captured before clearing). set clrts = 1 to clear this register (add 09h, pwr_v dd register). note that the time stamp regi sters are cleared to all ?0?, including the month and day, which is different from the rtc and alarm registers (those registers default to 01h). this is the indicator that no time stamping has occurred since the last clear or initial power-up. once a time stamp occurs, there will be a non- zero time stamp. time stamp battery to v dd registers (tsb2v) the time stamp battery to v dd register bytes are identical to the rtc register bytes, except they do not extend beyond month. the time stamp captures the last transition of v bat to v dd (only the last event of a series of power-up/power-down events is retained). set clrts = 1 to clear this register (add 09h, pwr_v dd register). alarm register bit description 76543210 hex sca0 00000000 00hseconds disabled mna0 10110000 b0hminutes set to 30, enabled hra0 10010001 91hhours set to 11, enabled dta0 10000001 81hdate set to 1, enabled moa0 10000001 81hmonth set to 1, enabled dwa0 00000000 00hday of week disabled table 21. alarm register bit description 76543210 hex sca0 10110000 b0hseconds set to 30, enabled mna0 00000000 00hminutes disabled hra0 00000000 00hhours disabled dta0 00000000 00hdate disabled moa0 00000000 00hmonth disabled dwa0 00000000 00hday of week disabled 60s rtc and alarm registe rs are both 30s figure 15. irq /f out waveform table 22. dst forward registers addressfunction76543210 20h month forward dste 0 0 mofd20 mofd13 mofd12 mofd11 mofd10 21h day forward 0 dwfde wkfd12 wkfd11 wkfd10 dwfd12 dwfd11 dwfd10 22h date forward 0 0 dtfd21 dtfd20 dtfd13 dtfd12 dtfd11 dtfd10 23h hour forward 0 0 hrfd21 hrfd20 hrfd13 hrfd12 hrfd11 hrfd10
isl12022ma fn7575 rev 5.00 page 23 of 31 september 5, 2012 dst control registers (dstcr) 8 bytes of control registers have been assigned for the daylight savings time (dst) functions. ds t beginning (set forward) time is controlled by the registers dstmofd, dstdwfd, dstdtfd, and dsthrfd. dst ending time (set backward or reverse) is controlled by dstmorv, dstdwrv, dstdtrv and dsthrrv. tables 22 and 23 describe the structure and functions of the dstcr. dst forward registers (20h to 23h) dst forward is controlled by the following dst registers: dst enable dste is the dst enabling bit located in bit 7 of register 20h (dstmofdxx). set dste = 1 will enable the dste function. upon powering up for the first time (i ncluding battery), the dste bit defaults to ?0?. when dste is se t to ?1? the rtc time must be at least one hour before the sche duled dst time change for the correction to take place. when dste is set to ?0?, the dstadj bit in the status register automatically resets to ?0?. dst month forward dstmofd sets the month that dst starts. the format is the same as for the rtc register month, from 1 to 12. the default value for the dst begin month is 00h. dst day/week forward dstdwfd contains both the day of the week and the week of the month data for dst forward control. dst can be controlled either by actual date or by setting both the week of the month and the day of the week. dstdwfde sets the priority of the day/week over the date. for dstdwfde = 1, day/week is the priority. you must have the correct day of week entered in the rtc registers for the day/week correction to work properly. ? bits 0, 1, 2 contain the day of the week information which sets the day of the week that dst starts. note that day of the week counts from 0 to 6, like the rtc registers. the default for the dst forward day of the week is 00h (normally sunday). ? bits 3, 4, 5 contain the week of the month information that sets the week that dst starts. the range is from 1 to 5, and week 7 is used to indicate the last w eek of the month. the default for the dst forward week of the month is 00h. dst date forward dstdtfd controls which date dst begins. the format for the date is the same as for the rtc register, from 1 to 31. the default value for dst forward date is 00h. dstdtfd is only effective if dstdwfde = 0. dst hour forward dsthrfd controls the hour that dst begins. the rtc hour and dsthrfd registers have the same formats except there is no military bit for dst hour. the user sets the dst hour with the same format as used for the rtc hour (am/pm or mil) but without the mil bit, and the dst will still advance as if the mil bit were there. the default value for dst hour forward is 00h. dst reverse registers (24h to 27h) dst end (reverse) is controlled by the following dst registers: dst month reverse dstmorv sets the month that dst ends. the format is the same as for the rtc register month, from 1 to 12. the default value for the dst end month is october (10h). dst day/week reverse dstdwrv contains both the day of the week and the week of the month data for dst reverse control. dst can be controlled either by actual date or by setting both th e week of the month and the day of the week. dstdwrve sets the priority of the day/week over the date. for dstdwrve = 1, day/week is the priority. you must have the correct day of week entered in the rtc registers for the day/week correction to work properly. ? bits 0, 1, 2 contain the day of the week information which sets the day of the week that dst en ds. note that day of the week counts from 0 to 6, like the rtc registers. the default for the dst reverse day of the week is 00h (normally sunday). ? bits 3, 4, 5 contain the week of the month information that sets the week that dst ends. the range is from 1 to 5, and week 7 is used to indicate the last week of the month. the default for the dst reverse week of the month is 00h. dst date reverse dstdtrv controls which date dst ends. the format for the date is the same as for the rtc register, from 1 to 31. the default value for dst date reverse is 00h. the dstdtrv is only effective if the dwrve = 0. dst hour reverse dsthrrv controls the hour that dst ends. the rtc hour and dsthrfd registers have the same formats except there is no military bit for dst hour. the us er sets the dst hour with the same format as used for the rtc hour (am/pm or mil) but without the mil bit, and the dst will still advance as if the mil bit were there. the default value for dst hour reverse is 00h. temp registers (temp) the temperature sensor produces an analog voltage output which is input to an a/d converter and produces a 10-bit table 23. dst reverse registers addressname 76543210 24h month reverse 0 0 0 morv20 morv13 morv12 morv11 morv10 25h day reverse 0 dwrve wkrv12 wkrv11 wkrv10 dwrv12 dwrv11 dwrv10 26h date reverse 0 0 dtrv21 dtrv20 dtrv13 dtrv12 dtrv11 dtrv10 27h hour reverse 0 0 hrrv21 hrrv2 0 hrrv13 hrrv12 hrrv11 hrrv10
isl12022ma fn7575 rev 5.00 page 24 of 31 september 5, 2012 temperature value in degrees kelvin. tk07:00 are the lsbs of the code, and tk09:08 are the msbs of the code. the temperature result is actually the average of two successive temperature measurements to produce greater resolution for the temperature control. the output code can be converted to c by first converting from binary to decimal, dividing by 2, and then subtracting 273d. the practical range for the temp sensor register output is from 446d to 726d, or -50c to +90c. the temperature compensation function is only guaranteed over -40c to +85c. the tse bit must be set to ?1? to enable temperature sensing. nppm registers (nppm) the nppm value is exactly 2x the net correction, in ppm, required to bring the oscillator to 0ppm er ror. the value is the combination of oscillator initial correction (ippm) and crystal temperature dependent correction (cppm). ippm is used to compensate the oscillator offset at room temperature and is controlled by th e itr0 and beta registers. this value is normally set during room temperature testing. the cppm compensates the oscillator frequency fluctuation over- temperature. it is determined by the temperature (t), crystal curvature parameter (alpha), an d crystal turnover temperature (xt0). t is the result of the temp sensor/adc conversion, whose decimal result is 2x the actual temperature in kelvin. alpha is from either the alpha (cold) or alphah (hot) register depending on t, and xt0 is from the xt0 register. nppm is governed by equations 4 and 5: nppm = ippm(itr0, beta) + alpha x (t-t0)2 where t is the reading of the adc, resu lt is 2 x temperature in degrees kelvin. or note that nppm can also be pr edicted from the fatr and fdtr register by the relationship (all values in decimal): nppm = 2*(beta*fatr - (fdtr-16) xt0 registers (xt0) turnover temperature (xt<3:0>) the apex of the alpha curve occurs at a point called the turnover temperature, or xt0. crystals normally have a turnover temperature between +20c and +30c, with most occurring near +25c. the isl12022ma has a preset turnover temperature corresponding to the crystal in the module. this value is recalled on initial power-up and is preset in device production. it is read only and cannot be overwritten by the user. table 26 shows the values available, with a range from +17.5c to +32.5c in +0.5c increments. the default value is 00000b or +25c. table 24. temp76543210 tk0l tk07 tk06 tk05 tk04 tk03 tk02 tk01 tk00 tk0m000000tk09tk08 temperature in c [(tk <9:0>)/2] - 273 = (eq. 3) nppm ippm cppm + = nppm ippm alpha t t0 C ?? ? 2 4096 --------------------------------------------------- - + = (eq. 4) alpha ? 2048 ? = t2298 ? ?? xt0 + = (eq. 5) t 596 xt0 + =
isl12022ma fn7575 rev 5.00 page 25 of 31 september 5, 2012 alpha hot register (alphah) the alpha hot variable is 7 bits and is defined as the temperature coefficient of crystal from the xt0 value to +85c (both alpha hot and alpha cold must be programmed to provide full temperature compensation). it is normally given in units of ppm/c 2 , with a typical value of -0.034. like th e alpha cold version, a scaled version of the absolute value of this coefficient is used in order to get an integer value. therefore, alp_h <7:0> is defined as the (|actual alpha hot value| x 2048) and converted to binary. for example, a crystal with alpha hot of -0.034ppm/c 2 is first scaled (|2048*(-0.034)| = 70d) and then converted to a binary number of 01000110b. the practical range of actual alphah values is from -0.020 to - 0.060. the isl12022ma has a preset alphah value corresponding to the crystal in the module. this value is recalled on initial power-up and is preset in device production. it is read only and cannot be overwritten by the user. user registers (accessed by using slave address 1010111x) addresses [00h to 7fh] these registers are 128 bytes of battery-backed user sram. the separate i 2 c slave address must be used to read and write to these registers. i 2 c serial interface the isl12022ma supports a bi-directional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and rece ive operations. therefore, the isl12022 ma operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state changes duri ng scl high are reserved for indicating start and stop conditio ns (see figure 16). on power- up of the isl12022ma, the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high. the isl12022ma continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 16). a start condition is ignored during the power-up sequence. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 16). a stop condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. 11001 20.5 11010 20.0 11011 19.5 11100 19.0 11101 18.5 11110 18.0 11111 17.5 table 27. alphah register addr76543210 2dh d alp_h 6 alp_h 5 alp_h 4 alp_h 3 alp_h 2 alp_h 1 alp_h 0 table 26. xt0 values (continued) xt<4:0> turnover temperature figure 16. valid data change s, start and stop conditions sda scl start data data stop stable change data stable
isl12022ma fn7575 rev 5.00 page 26 of 31 september 5, 2012 an acknowledge (ack) is a software convention used to indicate a successful data transfer. the tr ansmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 17). the isl12022ma responds with an ack after recognition of a start condition followed by a valid identification byte, and once again, after successful rece ipt of an address byte. the isl12022ma also responds with an ack after receiving a data byte of a write operation. the master must respond with an ack after receiving a data by te of a read operation. device addressing following a start condition, the master must output a slave address byte. the 7 msbs are the device identifiers. these bits are ?1101111? for the rtc registers and ?1010111? for the user sram. the last bit of the slave address byte defines a read or write operation to be performed. when this r/w bit is a ?1?, a read operation is selected. a ?0? selects a write operation (refer to figure 19). after loading the entire slave address byte from the sda bus, the isl12022ma compares the device identifier and device select bits with ?1101111? or ?1010111?. upon a correct compare, the device outputs an acknowledge on the sda line. following the slave byte is a one byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power-up, the internal address counter is set to address 00h, so a current address read starts at address 00h. when required, as part of a random read, the master must supply the 1 word address byte s, as shown in figure 20. in a random read operation, the slave byte in the ?dummy write? portion must match the slave byte in the ?read? section. for a random read of the control/status registers, the slave byte must be ?1101111x? in both places. write operation a write operation requires a start condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition. after each of the three bytes, the isl12022ma responds with an ack. at this time, the i 2 c interface enters a standby state. figure 17. acknowledge response from receiver figure 18. byte write sequence (slave address for csr shown) sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance s t a r t s t o p identification byte data byte a c k signals from the master signals from the isl12022ma a c k 10 0 11 a c k write signal at sda 0000 111 address byte slave address byte d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte a6 a5 1 10 1 1 1 r/w 1 word address
isl12022ma fn7575 rev 5.00 page 27 of 31 september 5, 2012 read operation a read operation consists of a th ree byte instruction, followed by one or more data bytes (see figu re 20). the master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to ?0?, an address byte, a second start, and a second identification byte with the r/w bit set to ?1?. after each of the th ree bytes, the isl12022ma responds with an ack. then the isl12022ma transmits data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of each byte. the master terminates the read operation (issuing a stop conditio n) following the last bit of the last data byte (see figure 20). the data bytes are from the memory location indicated by an internal pointer. this pointer?s in itial value is determined by the address byte in the read operation instruction, and increments by one during transmission of each data byte. after reaching the memory location 2fh, the pointer ?rolls over? to 00h, and the device continues to output data for each ack received. application section power supply considerations the isl12022m contains programm ed eeprom registers which are recalled to volatile ram registers during initial power-up. these registers contain dc voltage, freq uency and temperature calibration settings. initial power-up can be either application of v bat or v dd power, whichever is first. it is important that the initial power-up meet the power supply slew rate specification to avoid faulty eeprom power-up recall. also, any glitches or low voltage dc pauses should be avoided, as these may activate recall at a low voltage and load erroneous data into the calibration registers. note that a very slow vdd ramp rate (outside data sheet limits) will almost always trigger erroneous recall and should be avoided entirely. battery backup details the isl12022ma has automatic switchover to battery backup when the v dd drops below the v bat mode threshold. a wide variety of backup sources can be used, including standard and rechargeable lithium, super-capacitors, or regulated secondary sources. the serial interface is disabled in battery backup, while the oscillator and rtc registers are operational. the sram register contents are powered to preserve their contents as well. the input voltage range for v bat is 1.8v to 5.5v, but keep in mind the temperature compensation only operates for v bat >2.7v. note that the device is not guaranteed to operate with a v bat < 1.8v, so the battery should be changed before discharging to that level. it is strongly advised to mo nitor the low battery indicators in the status registers and take action to replace discharged batteries. if a supercapacitor is used, it is possible that it may discharge to below 1.8v during prolonged power-down. once powered up, the device may lose serial bus communications until both v dd and v bat are powered down together. to avoid that situation, including situations where a battery may discharge deeply, the circuit in figure 21 can be used. the diode, d bat will add a small drop to the battery voltage but will protect the circuit should battery voltage drop below 1.8v. the jumper is added as a safeguard should the battery ever need to be disconnected from the circuit. the v dd negative slew rate should be limited to below the data sheet spec (10v/ms) otherwise battery switchover can be delayed, resulting in sram cont ents corruption and oscillator operation interruption. some applications will require separate supplies for the rtc v dd and the i 2 c pull-ups. this is not advised, as it may compromise the operation of the i 2 c bus. for applications that do require serial bus communication with the rtc v dd powered down, the sda pin must be pulled low during the time the rtc v dd ramps down to 0v. otherwise, the device may lose serial bus communications once v dd is powered up, and will return to normal operation only once v dd and v bat are both powered down together. layout considerations the isl12020m contains a quartz crystal and requires special handling during pc board assembly. excessive shock and vibrations should be avoided. ultr asound cleaning is not advisable. see note 6 on page 6 in the electrical specific ations table pertaining to solder reflow effects on oscillator accuracy. figure 20. read sequence (csr slave address shown) signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 0 s t o p a c k 1 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 10 1 1111 10 1 11 11 figure 21. suggested battery backup circuit d bat c bat c in bat43w 0.1f 0.1f v dd = 2.7v v bat = 1.8v j bat isl12022ma vdd gnd vbat to 3.2v to 5.5v +
isl12022ma fn7575 rev 5.00 page 28 of 31 september 5, 2012 the part of the package from pin 4 to 6 and from pin 15 to 17 contains the crystal. low frequency rtc crystals are known to pick up noise very easily if layout precautions are not followed, even embedded within a plastic packag e. most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interf erence from adjacent high speed clock or data lines. careful layout of the rtc circuit will avoid noise pickup and insure accurate clocking. figure 22 shows a suggested layout for the isl12022ma device. the following main precau tions should be followed: ? do not run the serial bus lines or any high speed logic lines in the vicinity of pins 1 and 20, or under the package. these logic level lines can induce noise in the oscillator ci rcuit, causing misclocking. ? add a ground trace around the device with one end terminated at the chip ground. this guard ring will provide termination for emitted noise in the vicinity of the rtc device ? add a 0.1f decoupling capacitor at the device v dd pin, especially when using the 32.768khz f out function. the best way to run clock lines around the rtc is to stay outside of the ground ring by at least a few millimeters. also, use the v bat and v dd as guard ring lines as well, they can isolate clock lines from the oscillator section. in addition, if the irq /f out pin is used as a clock, it should be routed away from the rtc device as well. measuring oscillator accuracy the best way to analyze the is l12022ma frequency accuracy is to set the irq /f out pin for a specific frequency, and look at the output of that pin on a high accuracy frequency counter (at least 7 digits accuracy). note that the irq /f out is an drain output and will require a pull-up resistor. using the 1.0hz output frequency is the most convenient as the ppm error is expressed in equation 6: other frequencies may be used for measurement but the error calculation becomes more complex. use the f out output and a frequency counter for the most ac curate results. also, when the proper layout guidelines above are observed, the oscillator should start-up in most circuits in less than one second. temperature compensation operation the isl12022ma temperature comp ensation feature needs to be enabled by the user. this must be done in a specific order as follows. ? read register 0dh, the beta regi ster. this register contains the 5-bit beta trimmed value, which is automatically loaded on initial power-up. mask off the 5 lsb?s of the value just read. ? bit 7 of the beta register is the master enable control for temperature sense operation. set this to ?1? to allow continuous temperature frequency correction. frequency correction will then happen every 60 seconds with v dd applied. ? bits 5 and 6 of the beta register control temperature compensation in battery backup mode (see table 16). set the values for the operation desired. ? write back to register 0dh making sure not to change the 5 lsb values, and include the desired compensation control bits. note that every time the beta register is written with the tse bit = 1, a temperature compensation cycle is instigated and a new correction value will be loaded into the fatr/fdtr registers (if the temperature changed since the last conversion). also note that registers 0bh and 0ch, the itr0 and alpha registers, are read-only, and cannot be writte n to. also the value for beta is locked and cannot be changed with a write. however, it is still a good idea to do the bit masking when doing tse bit changes. daylight savings time (dst) example dst involves setting the forward and back times and allowing the rtc device to automatically adva nce the time or set the time back. this can be done for current year, and future years. many regions have dst rules that us e standard months, weeks and time of the day, which permit a pre-programmed, permanent setting. table 28 shows an example setup for the isl12022ma. figure 22. suggested layout for the isl12022ma f out scl sda ground ring ppm error f out 11e6 ? C = (eq. 6)
fn7575 rev 5.00 page 29 of 31 september 5, 2012 isl12022ma intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2010-2012. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. the enable bit (dste) is in the month forward register, so the bcd value for that register is altered with the additional bit. the week and day values along with week/day vs date select bit is in the week/day register, so that value is also not straight bcd. hour and month are normal bcd, but the ho ur doesn?t use the mil bit since military time pm values are already discretely different from am/pm time pm values. the dst reve rse setting utilizes the option to select the last week of the month for october, which could have 4 or 5 weeks but needs to have the time change on the last sunday. note that the dstadj bit in the status register monitors whether the dst forward adjustment has happened. when it is ?1?, dst forward has taken place. when it is ?0?, then either dst reverse has happened, or it has been reset either by initial power-up or if the dste bit has been set to ?0?. device handling precautions the isl12022ma contains a quartz crystal and requires special handling during pc board assembly. excessive shock and vibrations should be avoided, especially with automated handling equipment (see ?absolute maximum ratings? on page 6 for shock and vibration). avoid dropping onto hard surfaces, placing rubber floor mats in assembly areas will greatly reduce the risk of damage. pcb panel routing should be monitored to avoid generating vibrations at harmonics of the crystal frequency (32khz). if possible, router speed should be adjusted to mitigate this risk. ultrasound cleaning is not advisabl e as it subjects the crystal to resonance and possible failure. units subject to shock, vibration or ultrasound may sustain crystal failures in one of many modes, all of which will affect oscillator frequency accuracy or cause oscillator failure. see also note 6 on page 6 in the specifications tables, which pertains to solder reflow effects on oscillator accuracy. note that overheating the package, in exce ss of +260 for >30 sec, will cause damage to the crystal seal and compromise oscillator accuracy. table 28. dst example variable value register value month forward and dst enable april 15h 84h week and day forward and select day/week, not date 1st week and sunday 16h 48h date forward not used 17h 00h hour forward 2am 18h 02h month reverse october 19h 10h week and day reverse and select day/week, not date last week and sunday 1ah 78h date reverse not used 1bh 00h hour reverse 2am 1ch 02h
isl12022ma fn7575 rev 5.00 page 30 of 31 september 5, 2012 products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl12022ma to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change august 22, 2012 fn7575.5 corrected pin 4 in ?t ypical application circuit? on page 1 from "gnd" to "nc" to match ?pin configuration ? and ?pin descriptions? on page 2. august 7, 2012 fn7575.4 changed pin 1 from gnc to gnd on page 2. removed bullet left column above figure 22 on page 28 which read: "be sure to ground pins 6 and 15 as well as pin 8 as these all insure the integr ity of the device ground". may 16, 2012 fn7575.3 added new section header ?oscillator accuracy? on page 7 removed min/max of -5/5ppm for ?oscillator stability vs temperature? on page 7. added typ of 2ppm changed min/max for ?oscillator initial accuracy? on page 7 from -3/+3 ppm to -2/+8ppm added ?oscillator accuracy after reflow cycle? on page 7. added notes 17, 18 cross references where required to above specs. added note 19 to ?oscillator stability vs voltage? on page 7. added notes 17, 18 and 19 to end of spec table on page 8. ?layout considerations? on page 27. changed 1st sentence of 2nd paragraph from: "the part of the package that has nc pins from pin 4 to 6 and from pin 15 to 17 contains the crystal." to "the part of the package from pin 4 to 6 and from pin 15 to 17 contains the crystal." october 24, 2011 fn7575.2 ? on page 1, 1st paragraph, added ?backup battery current draw is less than 1.6a over the temperature r ange.? under features, added bullet ?1.6a max battery current? ? on page 6, dc operating characteristics: for i dd1 at 5v and 3v limits, changed max from 7a and 6a to 15a and 14a. ? on page 7, power-down timing: added v ddsr+ with typ value of 0.05v/ms, with reference to note 16. ? on page 8, added note 16 for v ddsr+ ? on page 13, oscillator compensation: text deleted: "these valu es can be overwritten by the user although this is not suggested as the resulting temperature compen sation performance will be compromised." ? on page 16, oscillator fail bit: changed text from "oscillator fail bit indicates that the oscillator has stopped." to: "oscillator fail bit indicates that the oscillator has failed. th e oscillator frequency is either zero or very far from the desired 32.768khz due to failure, pc board contamination or mechanical issues." ? on page 16, daylight saving time change bit (dstadj): removed "dstadj can be set to "1" for instances where the rtc device is initialized during the dst forward period." and added "it is read-only and cannot be written. setting time during a dst forward period will not set this bit to "1"." ? on page 21, table 20, fdtr column heading changed from <2:0> to <4:0> ? on page 27, added ?power su pply considerations? section. ? on page 27, added paragraph at beginning of layout considerations for handling. ? on page 31, package outline drawing: replaced m20.3, rev 2, 6/15, with m20.3, rev 3, 2/11. july 1, 2010 fn7575.1 in the ?device handling precautions? on pa ge 29, changed the max reflow temperature from ?+280c? to ?+260c for >30 sec? june 1, 2010 fn7575.0 initial release.
isl12022ma fn7575 rev 5.00 page 31 of 31 september 5, 2012 package outline drawing m20.3 20 lead wide body small outline plastic package (soic) rev 3, 2/11 7. the lead width as measured 0.36mm (0.14 inch) or greater a bove the seating plane, shall not exceed a maximum value of 0.61mm detail "x" side view typical recommended land pattern top view 13.00 0.75 0.25 x 45 0.32 0.23 max 8 1.27 0.40 10.65 10.00 7.60 7.40 20 123 index area 2.65 2.35 0.30 max bsc 1.27 0.35 0.49 0.25 (0.10) mc s b m a 0.10 (0.004) 0.25 (0.10) mb m 1 2 1.27 bsc (9.40mm) seating plane (0.60) (2.00) 2 20 3 3 5 7 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimension does not include mold flash, protrusions or gate 3. dimension does not include interlead lash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) pe r side. 4. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 5. dimension is the length of t erminal for soldering to a sub strate. 6. terminal numbers are shown for reference only. 8. controlling dimension: millimeter. 9. dimensions in ( ) for reference only. burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. (0.024 inch) 10. jedec reference drawing number: ms-013-ac. 12.60

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